1. FIELD OF THE INVENTION
This invention relates to a metal-insulator-semiconductor (MIS) logic circuit and more particularly to a MIS decoder circuit.
2. DESCRIPTION OF THE PRIOR ART
A variety of random access memories (referred to as RAM, herein below) formed in ICs have been developed along with the recent remarkable progresses in microcomputers. A representative example is the Intel 1103 1 kbit MOS dynamic IC memory. The decoder circuit of such a RAM utilizes the dynamic ratioless circuit and is formed of a plurality of address circuits including a NAND type logic circuit.
An example of such a conventional MOS decoder logic circuits will be described referring to FIGS. 1A to 1C.
FIG. 1A shows the circuit structure and FIGS. 1B and 1C show the timing waveforms of an information output operation in the case of the address selection mode.
In this circuit, at first, a first pulse P is applied to the gate of a metal-oxide-semiconductor field effect transistor (MOSFET) Q.sub.1. Then, a parasitic capacitor C.sub.o is charged with the voltage V.sub.DD (precharge period t.sub.1). In the address selection mode, no second pulses A to E are applied to the gates of the MOSFETS Q.sub.2 to Q.sub.6. Thus, the capacitor C.sub.o remains charged. Here, the first pulse no longer exists and the FET Q.sub.1 is turned off. Then, a third pulse CE such as a socalled chip enable signal is applied to the drain of the MOSFET Q.sub.7. As a result, a signal of a logic value "1" is derived from a word line WL on the source side of said MOSFET Q.sub.7. For discharging the word line, the gate of the MOSFET Q.sub.8 is applied with another pulse CE to bring it into the "on" state and hence to ground the word line WL.
Next, in the address non-selection mode, at least one second pulse as shown by A to E in FIG. 1B is applied to the gate of at least one MOSFET Q.sub.2 (sampling period t.sub.2). Therefore, the stored charge in the capacitor C.sub.o is discharged through the one turned-on MOSFET among the MOSFETS Q.sub.2 to Q.sub.6. At this time, the first pulse has already disappeared. When a third pulse CE is applied to the drain of the MOSFET Q.sub.7 (information outputting period t.sub.3), a signal of a logic "O" is derived from the word line WL connected to the source of the MOSFET Q.sub.7. In this way, the logical result of the MOS logic circuit Q.sub.2 to Q.sub.6 is stored in and read out from the capacitor C.sub.o.
In this way, the decoder circuit using the dynamic drive operates in a time sharing manner: in three periods made up of a charging period (t.sub.1), a sampling period (t.sub.2) and an information outputting period (t.sub.3). The dynamic ratioless circuit used in this circuit is described in Japanese Patent Publication No. 47463/1972 (based on U.S. Ser. No. 523,767 filed on Jan. 28, 1966 and U.S. Ser. No. 10,966 filed on Feb. 11, 1970 ) and has such advantages that the power consumption is small, and that there is no need to consider the voltage ratio of the MOSFETS constituting the circuit.
In such a conventional circuit, however, in the address non-selection mode, there is a possibility of generating a signal of a logic "1" on the word line unless the third pulse CE is applied after the charge stored on the capacitor C.sub.o has been completely discharged, as shown in FIG. 1C. Accordingly, there must be a sufficient delay in the input period of the third pulse CE as shown by the dotted line. Therefore, this leads to an elongated access time (FIG. 1C).
For solving these problems, the time constant for discharging the capacitor C.sub.o in the address non-selection mode should preferably be made small. For reducing the time constant, the "on" resistance of all the MOSFETS Q.sub.2 to Q.sub.6 should be made sufficiently small. Here, it is not desirable from the design of an integrated circuit to make the size of the MOSs in the respective logic blocks disposed in rows and columns different. Thus, it becomes necessary to reduce the resistance of all the MOSFETs Q.sub.2 to Q.sub.6 and to manufacture all the logic blocks with the same ratings.
According to the above method, however, the time required for completely discharging the capacitor C.sub.o cannot yet be precisely controlled. Hence, a malfunction may occur unless the third pulse CE is applied with a considerable time margin. Thus, the access time could not have been improved much.